For the connection of multiple semiconductor components, semiconductor chips can be arranged one next to the other and can be connected in an electrically conductive way to each other by wires, or multiple semiconductor chips can be arranged stacked vertically one above the other and can be connected to each other by electrical connection contacts on the top sides and bottom sides. When the semiconductor chips are stacked, electrically conductive connections must be established through the substrate from the top side of each chip to the bottom side. For this purpose, holes are typically etched into the substrate, wherein these holes are then filled with an electrically conductive material, typically a metal. If the electrical conductor is established so that it does not reach up to the back side of the substrate, then the substrate is thinned from the back side by grinding until the conductive material of the contact-hole filling is exposed and the via contact is created. On the surfaces of the substrate, metal layers can be deposited as connection metalization and can be structured corresponding to the provided connections. When the chips are stacked, the connection contact faces allocated to each other are arranged one above the other and are connected to each other permanently in an electrically conductive way, for example, by means of a solder. (J. Vardaman, “3-D Through-Silicon Vias Become a Reality,” Semiconductor International, Jun. 1, 2007)
Typical approaches create via contacts with diameters of 10 μm to 50 μm, wherein the contact holes are filled with copper (T. Rowbotham et al., “Back side exposure of variable size through silicon vias,” J. Vac. Sci. Techn. B24(5), 2006) or polycrystalline silicon (E. M. Chow et al., “Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates,” J. of Micromechanical Systems, Vol. 11, No. 6, 2002; J. H. Wu et al., “Through-Wafer Interconnect in Silicon for RFICs,” IEEE Trans. on El. Dev. 51, No. 11, 2004) or covered with organic material (N. Lietaer et al., “Development of cost-effective high-density through-wafer interconnects for 3-D microsystems,” J. of Micromechanics and Microengineering 16, S29-S34, 2006).
Large-dimensioned via contacts in semiconductor wafers are created, for example, through the etching of large cutouts with angled side walls, for example, under the use of KOH. A metal layer deposited in the cutout is exposed from the opposite top side of the wafer and is provided there with a contact. Conventional methods are described in US 2005/156330, US 2005/090096, U.S. Pat. Nos. 6,323,546, 6,483,147, 6,159,833, JP 2001 116768, U.S. Pat. Nos. 6,352,923, 6,252,300, 6,110,825, 5,511,428, and CA 1 057 411.